module reg_sender (
    input wire clk,
    input wire rst_n,
    input wire step_mode,
    input wire step,
    input wire step_done,              // 单步完成信号

    // FIFO 写接口
    output reg [7:0] fifo_din,    // 串口输出数据
    output reg fifo_write_en,     // 写使能（仅1周期）

    // 寄存器输入（编号 0~8）
    input wire [15:0] ACC, BR, MR, AX, BX, CX, DX,
    input wire [7:0] SP, PC,

    input wire fifo_full,         // FIFO 满标志
    output reg busy               // 正在发送中
);

    reg [3:0] send_index;         // 当前发送第几个寄存器
    reg [2:0] byte_state;         // 发送状态（0名称1，1名称2，2冒号，3高字节，4低字节，5逗号）
    reg sending;
    reg [15:0] current_data;

    // 主 FSM 控制逻辑
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            send_index      <= 0;
            byte_state      <= 0;
            fifo_write_en   <= 0;
            fifo_din        <= 8'd0;
            busy            <= 0;
            sending         <= 0;
            current_data    <= 16'd0;
        end else begin
            fifo_write_en <= 0; // 默认拉低，确保为脉冲

            if ((step_mode && step_done )||(!step_mode && step)&& !sending) begin
                sending     <= 1;
                send_index  <= 0;
                byte_state  <= 0;
                busy        <= 1;
            end else if (sending && !fifo_full) begin
                case (byte_state)
                    3'd0: begin // 发送寄存器名称第1个字符
                        case (send_index)
                            4'd0: fifo_din <= 8'h41; // 'A'
                            4'd1: fifo_din <= 8'h42; // 'B'
                            4'd2: fifo_din <= 8'h4D; // 'M'
                            4'd3: fifo_din <= 8'h41; // 'A'
                            4'd4: fifo_din <= 8'h42; // 'B'
                            4'd5: fifo_din <= 8'h43; // 'C'
                            4'd6: fifo_din <= 8'h44; // 'D'
                            4'd7: fifo_din <= 8'h53; // 'S'
                            4'd8: fifo_din <= 8'h50; // 'P'
                            default: fifo_din <= 8'h20; // ' '
                        endcase
                        fifo_write_en <= 1;
                        byte_state <= 1;
                    end
                    3'd1: begin // 发送寄存器名称第2个字符
                        case (send_index)
                            4'd0: fifo_din <= 8'h43; // 'C'
                            4'd1: fifo_din <= 8'h52; // 'R'
                            4'd2: fifo_din <= 8'h52; // 'R'
                            4'd3: fifo_din <= 8'h58; // 'X'
                            4'd4: fifo_din <= 8'h58; // 'X'
                            4'd5: fifo_din <= 8'h58; // 'X'
                            4'd6: fifo_din <= 8'h58; // 'X'
                            4'd7: fifo_din <= 8'h50; // 'P'
                            4'd8: fifo_din <= 8'h43; // 'C'
                            default: fifo_din <= 8'h20; // ' '
                        endcase
                        fifo_write_en <= 1;
                        byte_state <= 2;
                    end
                    3'd2: begin // 发送冒号
                        fifo_din <= 8'h3A; // ':'
                        fifo_write_en <= 1;
                        byte_state <= 3;
                        case (send_index)
                            4'd0: current_data <= ACC;
                            4'd1: current_data <= BR;
                            4'd2: current_data <= MR;
                            4'd3: current_data <= AX;
                            4'd4: current_data <= BX;
                            4'd5: current_data <= CX;
                            4'd6: current_data <= DX;
                            4'd7: current_data <= {8'b0, SP};
                            4'd8: current_data <= {8'b0, PC};
                            default: current_data <= 16'h0000;
                        endcase
                    end
                    3'd3: begin // 发送高第一字节
                        fifo_din <= ((current_data[15:12] < 4'd10) ?
                        (current_data[15:12] + 8'h30) : (current_data[15:12] - 4'd10 + 8'h41));
                        fifo_write_en <= 1;
                        byte_state <= 4;
                    end
                    3'd4: begin // 发送高第二字节
                        fifo_din <= ((current_data[11:8] < 4'd10) ?
                        (current_data[11:8] + 8'h30) : (current_data[11:8] - 4'd10 + 8'h41));
                        fifo_write_en <= 1;
                        byte_state <= 5;
                    end
                    3'd5: begin // 发送低第一字节
                        fifo_din <= ((current_data[7:4] < 4'd10) ?
                        (current_data[7:4] + 8'h30) : (current_data[7:4] - 4'd10 + 8'h41));
                        fifo_write_en <= 1;
                        byte_state <= 6;
                    end
                    3'd6: begin // 发送低第二字节
                        fifo_din <= ((current_data[3:0] < 4'd10) ?
                        (current_data[3:0] + 8'h30) : (current_data[3:0] - 4'd10 + 8'h41));
                        fifo_write_en <= 1;
                        byte_state <= 7;
                    end

                    3'd7: begin // 发送逗号或结束
                        if (send_index == 4'd8) begin
                            fifo_din <= 8'h0A; // 换行符 '\n'
                            fifo_write_en <= 1;
                            sending <= 0;
                            busy <= 0;
                        end else begin
                            fifo_din <= 8'h2C; // 逗号 ','
                            fifo_write_en <= 1;
                            send_index <= send_index + 1;
                            byte_state <= 0;
                        end
                    end
                endcase
            end
        end
    end
endmodule
